The present invention relates, in general, to tape automated bonding (TAB) tape interconnect structures, and more particularly to a TAB interconnect construction which facilitates burn-in and permits the use of a simplified burn-in socket.
Tape automated bonding is a well known technique for fabricating packaged integrated circuit semiconductor devices. Semiconductor integrated circuits chips, or dies, conventionally have multiple electrical contact points which are connected through external electrical leads or thin film conductors to plug-in contacts, to printed circuit boards, or the like. In production processes in which tape automated bonding is employed, a strip of metallized tape in reel form carries a plurality of groups of metallic fingers or lines which form interconnect lines, or conductors. The conductors are arranged in arrays to be connected at inner ends to contact points on the integrated circuits, as by compression bonding, for example, with the outer ends of the conductors then forming external contacts of an integrated circuit package.
Patents directed to this technique illustrate conductor arrays formed from a very thin flexible metallized tape having a typical thickness of 2.3 to 2.9 mils. The conductor array utilizes interconnecting links between the adjacent conductors to hold them in the desired spaced relationship. In addition, sprocket hole perforations are provided along the outer edges of the tape for indexing and moving the tape through fabrication stations. After the contact points on the integrated circuit are bonded to the inner ends of corresponding metallic conductors, the circuit chip and the bonded connections are encapsulated. The interconnecting links between the conductors are then sheared to produce a semiconductor chip package having conductors by which it can be connected to suitable equipment for testing to make sure it is operating properly. Such a device is illustrated, for example, in U.S. Pat. No. 3,611,061.
Later patents illustrate a two-layer tape wherein the finger-like conductor lines are formed, as by etching techniques, in a metal foil carried on an insulative tape. These lines are formed from a thin copper foil with a thickness of from about 1.0 to 1.6 mils, with the insulating tape providing a support for the thin lines during the mounting of the integrated circuit chip and bonding of the chip contact points with the ends of the lines on the tape. The tape can remain as a part of the final assembly to provide support for the conductors. Such a tape is illustrated, for example, in U.S. Pat. No. 3,689,991.
The integrated circuit packages produced in the foregoing manner may then be used in a variety of circuit configurations, often becoming a part of highly expensive and complex circuits where high reliability is essential. However, the probability of having all of the semiconductor devices in such a complex circuit functioning within specifications is quite low, and accordingly it is extremely important that each semiconductor device be tested before such assembly.
One of the important tests to be conducted on an integrated circuit semiconductor die is the so-called burn-in test, in which bias supply voltages are applied to the device for a predetermined duration of time. Power is applied to the various bias voltage leads of the semiconductor chip, with power being applied for sufficient period of time to raise the temperature of the semiconductor device to a relatively high temperature, at least equal to that which it would be expected to encounter in use. This heating of the device with the applied bias voltages is intended to produce failures in any weak semiconductor devices, so that these can be weeded out and discarded, leaving only the satisfactory devices for assembly in circuits, or for delivery to customers.
Many complex integrated circuit semiconductor dies have very high lead counts, often in excess of 300 leads. Since the dies are quite small, the leads are extremely close together; for example, they might have an 8 mil pitch, with a spacing of 8 mils center to center. This high count and close spacing makes it very difficult to fabricate test sockets for connecting the leads to external equipment for test purposes. One standard method has been to fan out the interconnect lines carried by the TAB support tape to provide a relatively large pitch between adjacent conductors, and then to build a test socket that will connect to these leads. However, high lead count semiconductor devices still require a large number of contact points on the test socket, and the high count requires a larger tape to accommodate all of the leads when fanned out, thus requiring an extraordinarily expensive, complex test socket as well as significantly increased tape cost.